1. Field of the Invention
The present invention relates to a failure analysis system of a semiconductor memory device.
2. Description of the Related Art
LSI failure analysis apparatuses commercially available from KLA-Tencor and Inspex in United States are conventionally known. These apparatuses are possible to analyze failure in case that about tens of thousands of fails exist on a wafer for semiconductor memory devices.
A memory LSI failure analysis apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 07-072206) corresponding to Japanese Patent No. 2629523. In this reference, a test result is sent from a memory tester to a personal computer. The know-how of the lay-out technical experts, process technical experts and circuit technical experts is implemented into the personal computer. The personal computer refers to the know-how of the experts to instruct the memory tester to carry out a next test. Thus, a fail cause of the LSI can be automatically found as is the test is carried out while the design technical expert carries on conversation with the memory tester. For this purpose, a bit map data from the tester is first classified by a main expert. Then, a sub-expert is started in accordance with the classifying result to automatically find the fail cause at short time. these results are statistically processed, and the factor determining a yield is analyzed. Thus, the yield can be improved.
Moreover, LSI failure analysis apparatuses are disclosed in U.S. patent application Ser. No. 09/219,349 by Sugimoto claiming the priority based on Japanese Patent Application (Tokuganhei 9-355926), and U.S. Pat application Ser. No. 09/475067 by Sugimoto, entitled “FAULT DISTRIBUTION ANALYZING SYSTEM” and claiming the priority based on Japanese Patent application (Tokuganhei 11-001680). In theses LSI failure analysis apparatuses, the intervals, kinds and frequencies of fail bits are analyzed and it is determined whether the fail bits are caused from the design of layout, circuit or circuit. The disclosures of these US Patent Applications are incorporated herein by reference.
In the above-mentioned conventional failure analysis apparatuses, an upper limit of analyzable fail bits in number is low. The capacity of a dynamic random access memory (hereinafter, to be referred to as a DRAM) which is assumed in the failure analysis apparatuses commercially available from KLA-Tencor and Inspex is 16 megabits or 64 megabits. Also, the number of chips in the DRAM is about a few hundreds on a single wafer having the diameter of 200 mm. Even if a fail bit density is supposed to be 10 ppm, that is, it is supposed that ten fail bits exist in a million bits, the number of fail bits exceeds 100,000 for every wafer. The capacity of a semiconductor memory device is further increased in future to achieve a high density. It is necessary to analyze fail bits of a DRAM having the capacity equal to or more than 256 megabits from now. In this case, the number of fail bits to be analyzed would be exponentially increased. For example, if the capacity is increased to 4 times and the number of chips is increased to 2.5 times by use of a large diameter wafer, the number of fail bits will be increased to 10 times. Therefore, in the conventional apparatuses, necessary and sufficient analysis can not be carried out. Using the conventional failure analysis apparatus, the number of analyzable wafers is decreased to {fraction (1/10)} or below so that the product yield would be decreased due to the delay of discovery of any fail cause.
Moreover, in these references, the processing to analyze the kinds and frequencies of divisors of the intervals between the fail bits is carried out the number of times equal to the number of combinations of the fail bits. Therefore, the load for the failure analysis would be increased proportionally to the square of the number of fail bits. Thus, when the number of fail bits is increased, the analysis time would be also increased. As a result, the decrease of the number of wafers to be analyzed and the degradation of the practicality can not be avoided.
In conjunction with the above description, a fail mode analysis apparatus of storage elements is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-187800). In the fail mode analysis apparatus of this reference, an analysis section (22) recognizes a fail bit map, which shows an operation test result of the storage elements, as a 2-dimensional image which has the same bit layout arrangement as that of the tested storage elements. The analysis section (22) analyzes a fail mode of the tested storage elements from the 2-dimensional image. A calculating section (23) calculates a sum of products of data of fail bit map in a small region and a data template for line failure which follows a fail bit arrangement. A determining section (24) determines a fail mode based on the calculation result. In this way, the fail mode of the tested storage element is analyzed based on the 2-dimensional image.
Also, a method of testing a semiconductor memory unit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-85697). In this reference, a fail bit is detected in a failure analysis system. Then, a specific fail mode is aimed at, and the fail bits corresponding to the specific fail mode are extracted based on a desired criterion to carry out a failure analysis. Also, various tests are implemented to the fail bits to which the classification of the fail modes has been accomplished, to specify a fail cause. As a result, the fail bits corresponding to the specific fail mode are extracted from the fail modes to make a failure analysis object clear.
Also, a semiconductor device failure analysis system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-124977). In a test data analytic system (101) of this reference, analysis is carried out based on the data obtained from a alien substance test (102) and outward appearance test (103) in a manufacturing line (111), the data obtained in a final wafer test (112) and the data from an FB analysis system (105). The FB analysis system (105) extracts a fail point and a fail causing point from a distribution of fail bits (FB) using the data obtained in the final wafer test (112) and an LSI design data (107). Then, the FB analysis system (105) refers to fail cause know-how data (108) to carry out the estimation (113) of a fail cause. An observing unit (109) observes coordinates of the fail point and the fail causing point which have been transferred from the FB analysis system (105) to specify a fail cause and a fail process. Also, an alien substance which has been detected by the observation unit (109) analyzes the component of an alien substance by an analysis apparatus (110) to specify the fail cause and the fail process.
In addition, a method of testing a memory test apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-222998). In this reference, the memory test apparatus (10) is composed of a failure analysis memory (5), a central processing unit (11) which carries out physical transformation and fail bit map display processing for every element, a display unit (12) which displays the position of a fail cell on a fail bit map for every element, and a storage unit (13) which stores the processing contents of the central processing unit (11). In the memory test apparatus (10), the semiconductor memory is tested and the positions of the fail cells are stored in the failure analysis memory (5). The fail bit maps are displayed from the data stored in the failure analysis memory (5) for every memory block, bit line, word line or other failure, based on a mask data which has been used in the process of a wafer process.